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Final Electrical Specifications
LT1738 Ultralow Noise DC/DC Controller
FEATURES
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DESCRIPTIO
March 2001
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Greatly Reduced Conducted and Radiated EMI Low Switching Harmonic Content Independent Control of Output Switch Voltage and Current Slew Rates Greatly Reduced Need for External Filters Single N-Channel MOSFET Driver 20kHz to 250kHz Oscillator Frequency Easily Synchronized to External Clock Regulates Positive and Negative Voltages Easier Layout Than with Conventional Switchers
APPLICATIO S
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Power Supplies for Noise Sensitive Communication Equipment EMI Compliant Offline Power Supplies Precision Instrumentation Systems Isolated Supplies for Industrial Automation Medical Instruments Data Acquisition Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT (R)1738 is a member of a new class of switching regulator controllers designed to lower conducted and radiated electromagnetic interference (EMI). Ultralow noise and EMI are achieved by controlling the voltage and current slew rates of an external N-channel MOSFET switch. Current and voltage slew rates can be independently set to optimize harmonic content of the switching waveforms vs efficiency. The LT1738 can reduce high frequency harmonic power by as much as 40dB with only minor losses in efficiency. The LT1738 utilizes a current mode architecture optimized for single switch topologies such as boost, flyback and Cuk. The IC includes gate drive and all necessary oscillator, control and protection circuitry. Unique error amp circuitry can regulate both positive and negative voltages. The internal oscillator may be synchronized to an external clock for more accurate placement of switching harmonics. Protection features include gate drive lockout for low VIN, soft-start, output current limit, short-circuit current limiting, gate drive overvoltage clamp and input supply undervoltage lockout.
TYPICAL APPLICATIO
5V VIN P3 22H
Ultralow Noise 5V to 12V Converter
MBRD620 B 10H 150F OSCON OPTIONAL 5pF 2
A 500V/DIV
A
12V Output Noise (Bandwidth = 100MHz)
12V 1A
+ 4 x 150F
OSCON 17 VIN 3 GCL CAP
+
+
100F 14 5 6 1.3nF 7 16.9k 25k 25k 3.6k 3.6k 8 16 15 12
SHDN V5 SYNC CT LT1738 RT RVSL RCSL VC SS 13 GND 11
GATE
1
Si9426
B 50mV/DIV
CS
4 25m
22nF
PGND FB NFB 10
20 21.5k 9
5s/DIV
1738 TA01a
0.22F
1.5k 10nF
2.5k
1738 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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400VP-P
1
LT1738
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GATE CAP GCL CS V5 SYNC CT RT FB 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 PGND NC NC VIN RVSL RCSL SHDN SS VC GND
Supply Voltage (VIN) ................................................ 20V Gate Drive Current ..................................... Internal Limit V5 Current ................................................. Internal Limit SHDN Pin Voltage .................................................... 20V Feedback Pin Voltage (Trans. 10ms) ...................... 10V Feedback Pin Current ............................................ 10mA Negative Feedback Pin Voltage (Trans. 10ms) ........ 10V CS Pin .......................................................................... 5V GCL Pin ..................................................................... 16V SS Pin .......................................................................... 3V Maximum Junction Temperature ......................... 125C Operating Temperature Range (Note 3) .............................................. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1738EG LT1738IG
NFB 10
G PACKAGE 20-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 110C/ W
Consult factory for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and other pins open unless otherwise noted.
SYMBOL VREF IFB FBREG VNFR INFR NFBREG gm IESK IESRC VCLH VCLL AV FBOV ISS PARAMETER Reference Voltage Feedback Input Current Reference Voltage Line Regulation Negative Feedback Reference Voltage Negative Feedback Input Current Negative Feedback Reference Voltage Line Regulation Error Amplifier Transconductance Error Amp Sink Current Error Amp Source Current Error Amp Clamp Voltage Error Amp Clamp Voltage Error Amplifier Voltage Gain FB Overvoltage Shutdown Soft-Start Charge Current Outputs Drivers Disabled VSS = 1V CONDITIONS Measured at Feedback Pin VFB = VREF 2.7V VIN 20V Measured at Negative Feedback Pin with Feedback Pin Open VNFB = VNFR 2.7V VIN 20V IC = 50A
q q q q q q
ELECTRICAL CHARACTERISTICS
MIN 1.235
TYP 1.250 250 0.003
MAX 1.265 1000 0.01 -2.45
UNITS V nA %/V V A
Error Amplifiers
-2.56 -37 1100 700 120 120
- 2.50 - 25 0.002 1500 200 200 1.27 0.12
0.01 2200 2500 350 350
mho mho A A V V V/V V
VFB = VREF + 150mV, VC = 0.9V VFB = VREF - 150mV, VC = 0.9V High Clamp, VFB = 1V Low Clamp, VFB = 1.5V
q q
180
250 1.47 9.0 12
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%/V A
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LT1738
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and other pins open unless otherwise noted.
SYMBOL fMAX fSYNC VSYNC RSYNC Gate Drive DCMAX VGON VGOFF IGSO IGSK VINUVLO Maximum Switch Duty Cycle Gate On Voltage Gate Off Voltage Max Gate Source Current Max Gate Sink Current Gate Drive Undervoltage Lockout (Note 5) RVSL = RCSL = 3.9k, Osc Frequency = 25kHz VIN = 12, GCL = 12 VIN = 12, GCL = 8 VIN = 12V VIN = 12V VIN = 12V VGCL = 6.5V 0.3 0.3 7.3 7.5
q
ELECTRICAL CHARACTERISTICS
PARAMETER Max Switch Frequency Synchronization Frequency Range SYNC Pin Input Threshold SYNC Pin Input Resistance
CONDITIONS
MIN
TYP 250
MAX
UNITS kHz kHz
Oscillator and Sync Oscillator Frequency = 250kHz
q
290 0.9 1.4 40 90 10 7.6 93.5 10.4 7.9 0.2 10.7 8.1 0.35 1.8
k % V V V A A V V V ns 120 300 mV mV V/s V/s V/s V/s 3.6 40 55 1.48 180 35 5.20 5.15 V mA mA V mV A V V mA mA
Current Sense tIBL VSENSE VSENSEF VSLEWR VSLEWF VISLEWR VISLEWF VINMIN IVIN VSHDN VSHDN ISHDN V5 IV5SC Switch Current Limit Blanking Time Sense Voltage Shutdown Voltage Sense Voltage Fault Threshold Output Voltage Slew Rising Edge Output Voltage Slew Falling Edge Output Current Slew Rising Edge (CS pin V) Output Current Slew Falling Edge (CS pin V) Minimum Input Voltage (Note 4) Supply Current (Note 3) Shutdown Turn-On Threshold Shutdown Turn-On Voltage Hysteresis Shutdown Input Current Hysteresis 5V Reference Voltage 5V Reference Short-Circuit Current 6.5V VIN 20V, IV5 = 5mA 6.5V VIN 20V, IV5 = - 5mA VIN = 6.5V Source VIN = 6.5V Sink RVSL = RCSL = 17k RVSL = RCSL = 17k RVSL = RCSL = 17k RVSL = RCSL = 17k VGCL = VIN RVSL = RCSL = 17k RVSL = RCSL = 17k VIN = 12 VIN = 20
q q q q q
100 VC Pulled Low
q
86
103 220 26 19 2.1 2.1 2.55 12 35
Slew Control for the Following Slew Tests See Test Circuit in Figure 1b
Supply and Protection
1.31 50 10 4.85 4.80 10 -10
1.39 110 24 5 5
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Supply current specification includes loads on each gate as in Figure 1a. Actual supply currents vary with operating frequency, operating voltages, V5 load, slew rates and type of external FET. Note 3: The LT1738E is guaranteed to meet performance specifications from 0C to 70C. Specifications from -40C to 85C are assured by
design, characterization and correlation with statistical process controls.The LT1738I is guaranteed and tested to meet performance specifications from - 40C to 85C. Note 4: Output gate drive is enabled at this voltage. The GCL voltage will also determine driver activity. Note 5: Gate drive is ensured to be on when VIN is greater than max value.
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LT1738 TYPICAL PERFOR A CE CHARACTERISTICS
Feedback Voltage and Input Current vs Temperature
1.260 1.258 1.256 750 NEGATIVE FEEDBACK VOLTAGE (V) 700 650 600 550 500 450 400 350 300 0 250 25 50 75 100 125 150 TEMPERATURE (C)
1683 G01
FEEDBACK VOLTAGE (V)
1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240 -50 -25
Feedback Overvoltage Shutdown vs Temperature
1.70 1.65 1.60 FEEDBACK VOLTAGE (V) 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1683 G03
TRANSCONDUCTANCE (mho)
1600 1500 1400 1300 1200 1100 1000 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1683 G04
CURRENT (A)
VC Pin Threshold and Clamp Voltage vs Temperature
1.4 1.2 VC PIN VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 -50 -25 THRESHOLD CLAMP 220 CS PIN VOLTAGE (mV) 200 180 160 140 120 240
SHDN PIN VOLTAGE (V)
0
25 50 75 100 125 150 TEMPERATURE (C)
1683 G06
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Negative Feedback Voltage and Input Current vs Temperature
2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 -50 -25 0 3.2 3.0 NFB INPUT CURRENT (A) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 25 50 75 100 125 150 TEMPERATURE (C)
1683 G02
Error Amp Transconductance vs Temperature
2000 1900 1800 1700 500 400 300 200 100 0 -100 -200 -300 -400
CS Pin Trip and CS Fault Voltage vs Temperature
1.50
FB INPUT CURRENT (nA)
FAULT TRIP 0
Error Amp Output Current vs Feedback Pin Voltage from Nominal
-40C 25C 125C
-500 -400 -300 -200 -100 0 100 200 300 400 FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)
1683 G05
SHDN Pin On and Off Thresholds vs Temperature
1.45 ON 1.40
1.35
1.30
100 80 -50 -25 25 50 75 100 125 150 TEMPERATURE (C)
1683 G07
OFF
1.25 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1683 G08
LT1738 TYPICAL PERFOR A CE CHARACTERISTICS
SHDN Pin Hysteresis Current vs Temperature
27 25 SHDN PIN CURRENT (A) 23 21 19 17 15 -50 -25
VIN CURRENT (mA)
15 14 13 12
VC PIN VOLTAGE (V)
0
25 50 75 100 125 150 TEMPERATURE (C)
1683 G09
Slope Compensation
110 GATE DRIVE A/B PIN VOLTAGE (V) PERCENT OF MAX CS VOLTAGE 100 90 80 70 60 50 VC PIN = 0.9V TA = 25C 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 9.90 9.80 0 20 40 60 DUTY CYCLE (%) 80 100
1683 G12
GCL = 12V
6.3 6.2 VIN = 12V NO LOAD 6.1 6.0 5.9
GATE DRIVE A/B PIN VOLTAGE (V)
Gate Drive Undervoltage Lockout Voltage vs Temperature
7.3 7.2 7.1 SS PIN CURRENT (V) VIN PIN VOLTAGE (V) 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1683 G15
GCL = 6V
8.9 8.7 8.5 8.3 8.1 7.9 7.7 7.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1683 G16
V5 PIN VOLTAGE (V)
UW
VIN Current vs Temperature
18 17 16 VIN = 20 RVSL, RCSL = 17k VIN = 12 RVSL, RCSL = 4.85k
CS Pin to VC Pin Transfer Function
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 CS PIN VOLTAGE (mV) 100 120
1683 G11
TA = 25C
VIN = 12 RVSL, RCSL = 17k
11 USING LOAD OF FIGURE 1A fOSC = 120kHz 10 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1738 G10
Gate Drive High Voltage vs Temperature
6.5 6.4 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05
Gate Drive Low Voltage vs Temperature
VIN = 12V NO LOAD
GCL = 6V
5.8 5.7 5.6
9.70 -50 -25
0
5.5 25 50 75 100 125 150 TEMPERATURE (C)
1683 G13
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1683 G14
Soft-Start Current vs Temperature
9.5 9.3 9.1 SS VOLTAGE = 0.9V 5.06 5.04 5.02 5.00 5.08
V5 Voltage vs Load Current
T = 125C
T = 25C
T = -40C 4.98 4.96 -15
-10
-5 0 5 LOAD CURRENT (mA)
10
15
1683 G17
5
LT1738
PI FU CTIO S
Part Supply
V5 (Pin 5): This pin provides a 5V output that can sink or source 10mA for use by external components. V5 source current comes from VIN . Sink current goes to GND. VIN must be greater than 6.5V in order for this voltage to be in regulation. If this pin is used, a small capacitor (<1F) may be placed on this pin to reduce noise. This pin can be left open if not used. GND (Pin 11): Signal Ground. The internal error amplifier, negative feedback amplifier, oscillator, slew control circuitry, V5 regulator, current sense and the bandgap reference are referred to this ground. Keep the connection to this pin, the feedback divider and VC compensation network free of large ground currents. SHDN (Pin 14): The shutdown pin can disable the switcher. Grounding this pin will disable all internal circuitry. Increasing SHDN voltage will initially turn on the internal bandgap regulator. This provides a precision threshold for the turn on of the rest of the IC. As SHDN increases past 1.39V the internal LDO regulator turns on, enabling the control and logic circuitry. 24A of current is sourced out of the pin above the turn on threshold. This can be used to provide hysteresis for the shutdown function. The hysteresis voltage will be set by the Thevenin resistance of the resistor divider driving this pin times the current sourced out. Above approximately 2.1V the hysteresis current is removed. There is approximately 0.1V of voltage hysteresis on this pin as well. The pin can be tied high (to VIN for instance). VIN (Pin 17): Input Supply. All supply current for the part comes from this pin including gate drive and V5 regulator. Charge current for gate drive can produce current pulses of hundreds of milliamperes. Bypass this pin with a low ESR capacitor. When VIN is below 2.55V the part will go into supply undervoltage lockout where the gate driver is driven low. This, along with gate drive undervoltage lockout, prevents unpredictable behavior during power up. PGND (Pin 20): Power Driver Ground. This ground comes from the MOSFET gate driver. This pin can have several hundred milliamperes of current on it when the external MOSFET is being turned off.
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Oscillator
SYNC (Pin 6): The SYNC pin can be used to synchronize the part to an external clock. The oscillator frequency should be set close to the external clock frequency. Synchronizing the clock to an external reference is useful for creating more stable positioning of the switcher voltage and current harmonics. This pin can be left open if not used. CT (Pin 7): The oscillator capacitor pin is used in conjunction with RT to set the oscillator frequency. For RT = 16.9k: COSC(nf) = 129/fOSC(kHz) RT (Pin 8): A resistor to ground sets the charge and discharge currents of the oscillator capacitor. The nominal value is 16.9k. It is possible to adjust this resistance 25% to set oscillator frequency more accurately.
Gate Drive
GATE (Pin 1): This pin connects to the gate of an external N-channel MOSFET. This driver is capable of sinking and sourcing at least 300mA. The GCL pin sets the upper voltage of the gate drive. The GATE pin will not be activated until VIN reaches a minimum voltage as defined by the GCL pin (gate undervoltage lockout). The gate drive output has current limit protection to safe guard against accidental shorts. GCL (Pin 3): This pin sets the maximum gate voltage to the GATE pin to the MOSFET gate drive. This pin should be either tied to a Zener, a voltage source, or VIN. If the pin is tied to a Zener or a voltage source, the maximum gate drive voltage will be approximately VGCL - 0.2V. If it is tied to VIN, the maximum gate voltage is approximately VIN - 1.6.
LT1738
PI FU CTIO S
Approximately 50A of current can be sourced from this pin if VGCL < VIN - 0.8V. This pin also controls undervoltage lockout of the gate drives. If the pin is tied to a Zener or voltage source, the gate drive will not be enabled until VIN > VGCL + 0.8V. If this pin is tied to VIN, then undervoltage lockout is disabled. There is an internal 19V Zener tied from this pin to ground to provide a fail-safe for maximum gate voltage. exceed the voltage on SS. Thus peak current will ramp up as the SS pin ramps up. During a short circuit fault the SS pin will be discharged to ground thus reinitializing softstart. When SS is below the VC clamp voltage the VC pin will closely track the SS pin. This pin can be left open if not used. CS (Pin 4): This is the input to the current sense amplifier. It is used for both current mode control and current slewing of the external MOSFET. Current sense is accomplished via a sense resistor (RS) connected from the source of the external MOSFET to ground. CS is connected to the top of RS. Current sense is referenced to the GND pin. The switch maximum operating current will be equal to 0.1V/RS. At CS = 0.1V, the gate driver will be immediately turned off (no slew control). If CS = 0.22V in addition to the drivers being turned off, VC and SS will be discharged to ground (short-circuit protection). This will hasten turn off on subsequent cycles. FB (Pin 9): The feedback pin is used for positive voltage sensing. It is the inverting input to the error amplifier. The noninverting input of this amplifier connects internally to a 1.25V reference. If the voltage on this pin exceeds the reference by 220mV, then the output driver will immediately turn off the external MOSFET (no slew control). This provides for output overvoltage protection When this input is below 0.9V then the current sense blanking will be disabled. This will assist start up. NFB (Pin 10): The negative feedback pin is used for sensing a negative output voltage. The pin is connected to the inverting input of the negative feedback amplifier through a 100k source resistor. The negative feedback amplifier provides a gain of -0.5 to the FB pin. The nominal regulation point would be -2.5V on NFB. This pin should be left open if not used. If NFB is being used then overvoltage protection will occur at 0.44V below the NFB regulation point. At NFB < -1.8 current sense blanking will be disabled.
Slew Control
CAP (Pin 2): This pin is the feedback node for the external voltage slewing capacitor. Normally a small 1pf to 5pf capacitor is connected from this pin to the drain of the MOSFET. The voltage slew rate is inversely proportional to this capacitance and proportional to the current that the part will sink and source on this pin. That current is inversely proportional to RVSL. RCSL (Pin 15): A resistor to ground sets the current slew rate for the external drive MOSFET during switching. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states of the MOSFET current will determine how the di/dt related harmonics are reduced. This time is proportional to RCSL and RS (the current sense resistor) and maximum current. Longer times produce a greater reduction of higher frequency harmonics. RVSL (Pin 16): A resistor to ground sets the voltage slew rate for the drain of the external drive MOSFET. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states on the MOSFET drain voltage will determine how dv/dt related harmonics are reduced. This time is proportional to RVSL, CV and the input voltage. Longer times produce more rolloff of harmonics. CV is the equivalent capacitance from CAP to the drain of the MOSFET.
Switch Mode Control
SS (Pin 3): The SS pin allows for ramping of the switch current threshold at startup. Normally a capacitor is placed on this pin to ground. An internal 9A current source will charge this capacitor up. The voltage on the VC pin cannot
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LT1738
PI FU CTIO S
VC (Pin 12): The compensation pin is used for frequency compensation and current limiting. It is the output of the error amplifier and the input of the current comparator. Loop frequency compensation can be performed with an RC network connected from the VC pin to ground. The voltage on VC is proportional to the switch peak current. The normal range of voltage on this pin is 0.25V to 1.27V. However, during slope compensation the upper clamp voltage is allowed to increase with the compensation. During a short-circuit fault the VC pin will be discharged to ground.
BLOCK DIAGRA
+ -
NFB 100k NEGATIVE FEEDBACK AMP 50k
+
1.25V CVC VC
CSS SS COMP
RT
RT OSCILLATOR CT
CT
SYNC
8
-
+
FB
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TEST CIRCUITS
20mA 5pF CAP IN5819 CAP GATE GATE ZVN3306A 2 10 CS 0.1 10 Si4450DY 5pF 0.9A IN5819
+ -
1738 F01a
+ -
1738 F01b
Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew
VIN CIN RCSL SHDN VIN V5 RCSL RVSL RVSL
TO DRIVERS REGULATOR
VREG
GCL CV CAP GATE
ERROR AMP
SLEW CONTROL
PGND
+ + -
S FF R Q SENSE AMP CS RSENSE
-
SUB
GND
1738 BD
LT1738
OPERATIO
In noise sensitive applications switching regulators tend to be ruled out as a power supply option due to their propensity for generating unwanted noise. When switching supplies are required due to efficiency or input/output constraints, great pains must be taken to work around the noise generated by a typical supply. These steps may include pre and post regulator filtering, precise synchronization of the power supply oscillator to an external clock, synchronizing the rest of the circuit to the power supply oscillator or halting power supply switching during noise sensitive operations. The LT1738 greatly simplifies the task of eliminating supply noise by enabling the design of an inherently low noise switching regulator power supply. The LT1738 is a fixed frequency, current mode switching regulator with unique circuitry to control the voltage and current slew rates of the output switch. Current mode control provides excellent AC and DC line regulation and simplifies loop compensation. Slew control capability provides much greater control over the power supply components that can create conducted and radiated electromagnetic interference. Compliance with EMI standards will be an easier task and will require fewer external filtering components. The LT1738 uses an external N-channel MOSFET as the power switch. This allows the user to tailor the drive conditions to a wide range of voltages and currents. CURRENT MODE CONTROL Referring to the block diagram. A switching cycle begins with an oscillator discharge pulse, which resets the RS flip-flop, turning on the GATE driver and the external MOSFET. The switch current is sensed across the external sense resistor and the resulting voltage is amplified and compared to the output of the error amplifier (VC pin). The driver is turned off once the output of the current sense amplifier exceeds the voltage on the VC pin. In this way pulse by pulse current limit is achieved. Internal slope compensation is provided to ensure stability under high duty cycle conditions. Output regulation is obtained using the error amp to set the switch current trip point. The error amp is a
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transconductance amplifier that integrates the difference between the feedback output voltage and an internal 1.25V reference. The output of the error amp adjusts the switch current trip point to provide the required load current at the desired regulated output voltage. This method of controlling current rather than voltage provides faster input transient response, cycle-by-cycle current limiting for better output switch protection and greater ease in compensating the feedback loop. The VC pin is used for loop compensation and current limit adjustment. During normal operation the VC voltage will be between 0.25V and 1.27V. An external clamp on VC or SS may be used for lowering the current limit. The negative voltage feedback amplifier allows for direct regulation of negative output voltages. The voltage on the NFB pin gets amplified by a gain of - 0.5 and driven on to the FB input, i.e., the NFB pin regulates to -2.5V while the amplifier output internally drives the FB pin to 1.25V as in normal operation. The negative feedback amplifier input impedance is 100k (typ) referred to ground. Soft-Start Control of the switch current during start up can be obtained by using the SS pin. An external capacitor from SS to ground is charged by an internal 9A current source. The voltage on VC cannot exceed the voltage on SS. Thus as the SS pin ramps up the VC voltage will be allowed to ramp up. This will then provide for a smooth increase in switch maximum current. SS will be discharged as a result of the CS voltage exceeding the short circuit threshold of approximately 0.22V. Slew Control Control of output voltage and current slew rates is achieved via two feedback loops. One loop controls the MOSFET drain dV/dt and the other loop controls the MOSFET dI/dt. The voltage slew rate uses an external capacitor between CAP and the MOSFET drain. This integrating cap closes the voltage feedback loop. The external resistor RVSL sets the current for the integrator. The voltage slew rate is thus inversely proportional to both the value of capacitor and RVSL.
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LT1738
OPERATIO
The current slew feedback loop consists of the voltage across the external sense resistor, which is internally amplified and differentiated. The derivative is limited to a value set by RCSL. The current slew rate is thus inversely proportional to both the value of sense resistor and RCSL. The two control loops are combined internally so that a smooth transition from current slew control to voltage slew control is obtained. When turning on, the driver current will slew before voltage. When turning off, voltage will slew before current. In general it is desirable to have RVSL and RCSL of similar value. Internal Regulator Most of the control circuitry operates from an internal 2.4V low dropout regulator that is powered from VIN. The internal low dropout design allows VIN to vary from 2.7V to 20V with stable operation of the controller. When SHDN < 1.3V the internal regulator is completely disabled. 5V Regulator A 5V regulator is provided for powering external circuitry. This regulator draws current from VIN and requires VIN to be greater than 6.5V to be in regulation. It can sink or source 10mA. The output is current limited to prevent against destruction from accidental short circuits. Safety and Protection Features There are several safety and protection features on the chip. The first is overcurrent limit. Normally the gate driver will go low when the output of the internal sense amplifier exceeds the voltage on the VC pin. The VC pin is clamped such that maximum output current is attained when the CS pin voltage is 0.1V. At that level the outputs will be immediately turned off (no slew). The effect of this control is that the output voltage will foldback with overcurrent. In addition, if the CS voltage exceeds 0.22V, the VC and SS pins will be discharged to ground, resetting the soft-start function. Thus if a short is present this will allow for faster MOSFET turnoff and less MOSFET stress. If the voltage on the FB pin exceeds regulation by approximately 0.22V, the outputs will immediately go low. The implication is that there is an overvoltage fault.
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The voltage on GCL determines two features. The first is the maximum gate drive voltage. This will protect the MOSFET gate from overvoltage. With GCL tied to a Zener or an external voltage source then the maximum gate driver voltage is approximately VGCL - 0.2V. If GCL is tied to VIN, then the maximum gate voltage is determined by VIN and is approximately VIN - 1.6V. There is an internal 19V Zener on the GCL pin that prevents the gate driver pin from exceeding approximately 19V. In addition, the GCL voltage determines undervoltage lockout of the gate drive. This feature disables the gate driver if VIN is too low to provide adequate voltage to turn on the MOSFET. This is helpful during start up to insure the MOSFET has sufficient gate drive to saturate. If GCL is tied to a voltage source or Zener less than 6.8V, the gate driver will not turn on until VIN exceeds GCL voltage by 0.8V. For VGCL above 6.5V, the gate drive is insured to be off for VIN < 7.3V and it will be turned on by VGCL + 0.8V. If GCL is tied to VIN, the gate driver is always on (undervoltage lockout is disabled). The gate drive has current limits for the drive currents. If the sink or source current is greater than 300mA then the current will be limited. The V5 regulator also has internal current limiting that will only guarantee 10mA output current. There is also an on chip thermal shutdown circuit that will turn off the output in the event the chip temperature rises to dangerous levels. Thermal shutdown has hysteresis that will cause a low frequency (<1kHz) oscillation to occur as the chip heats up and cools down. The chip has an undervoltage lockout feature that will force the gate driver low in the event that VIN drops below 2.5V. This insures predictable behavior during start up and shut down. SHDN can be used in conjuction with an external resistor divider to completely disable the part if the input voltage is too low. This can be used to insure adequate voltage to reliably run the converter. See the section in Applications Information. Table 1 summarizes these features.
LT1738
OPERATIO
FEATURE
Table 1. Safety and Protection Features
FUNCTION Turn Off FET at Maximum Switch Current (VSENSE = 0.1) Turn Off FET and Reset VC for Short-Circuit (VSENSE = 0.22) EFFECT on GATE DRIVER Immediately Goes Low Immediately Goes Low SLEW CONTROL EFFECT on VC, SS Overridden Overridden Overridden None Overridden Overridden Overridden None None None Discharge VC, SS to GND None None None None None None None Maximum Current Fault Short-Circuit Fault Overvoltage Fault GCL Clamp Gate Drive Undervoltage Lockout Thermal Shutdown VIN Undervoltage Lockout Gate Drive Source and Sink Current Limit V5 Source/Sink Current Limit Shutdown
APPLICATIO S I FOR ATIO
Reducing EMI from switching power supplies has traditionally invoked fear in designers. Many switchers are designed solely on efficiency and as such produce waveforms filled with high frequency harmonics that then propagate through the rest of the system. The LT1738 provides control over two of the more important variables for controlling EMI with switching inductive loads: switch voltage slew rate and switch current slew rate. The use of this part will reduce noise and EMI over conventional switch mode controllers. Because these variables are under control, a supply built with this part will exhibit far less tendency to create EMI and less chance of encountering problems during production. It is beyond the scope of this data sheet to get into EMI fundamentals. Application Note 70 contains much information concerning noise in switching regulators and should be consulted. Oscillator Frequency The oscillator determines the switching frequency and therefore the fundamental positioning of all harmonics. The use of good quality external components is important to ensure oscillator frequency stability. The oscillator is of
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Turn Off Driver If FB > VREG + 0.22V Immediately Goes Low (Output Overvoltage) Set Max Gate Voltage to Prevent FET Gate Breakdown Disable Gate Drive When VIN Is Too Low. Set Via GCL Pin Turn Off Driver If Chip Temperature Is Too Hot Disable Part When VIN 2.55V Limit Gate Drive Current Limit Current from V5 Disable Part When SHDN <1.3V Limits Max Voltage Immediately Goes Low Immediately Goes Low Immediately Goes Low Limit Drive Current None
a sawtooth design. A current defined by external resistor RT is used to charge and discharge the capacitor CT . The discharge rate is approximately ten times the charge rate. By allowing the user to have control over both components, trimming of oscillator frequency can be more easily achieved. The external capacitance CT is chosen by:
C T (nF ) =
2180 f(kHz)* RT (k)
where f is the desired oscillator frequency in kHz. For RT equal to 16.9k, this simplifies to:
C T (nF ) =
129 f(kHz)
e.g., CT = 1.29nF for f = 100kHz Nominally RT should be 16.9k. Since it sets up current, its temperature coefficient should be selected to compliment the capacitor. Ideally, both should have low temperature coefficients.
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LT1738
APPLICATIO S I FOR ATIO
Oscillator frequency is important for noise reduction in two ways. First the lower the oscillator frequency the lower the waveform's harmonics, making it easier to filter them. Second the oscillator will control the placement of the output voltage harmonics which can aid in specific problems where you might be trying to avoid a certain frequency bandwidth. Oscillator Sync If a more precise frequency is desired (e.g., to accurately place harmonics) the oscillator can be synchronized to an external clock. Set the RC timing components for an oscillator frequency 10% lower than the desired sync frequency. Drive the SYNC pin with a square wave (with greater than 1.4V amplitude). The rising edge of the sync square wave will initiate clock discharge. The sync pulse should have a minimum pulse width of 0.5s. Be careful in sync'ing to frequencies much different from the part since the internal oscillator charge slope determines slope compensation. It would be possible to get into subharmonic oscillation if the sync doesn't allow for the charge cycle of the capacitor to initiate slope compensation. In general, this will not be a problem until the sync frequency is greater than 1.5 times the oscillator free-run frequency. Slew Rate Setting The primary reason to use this part is to gain advantage of lower EMI and noise due to the slew control. The rolloff in higher frequency harmonics has its theoretical basis with two primary components. First, the clock frequency sets the fundamental positioning of harmonics and second, the associated normal frequency rolloff of harmonics. This part creates a second higher frequency rolloff of harmonics that inversely depends on the slew time, the time that voltage or current spends between the off state and on state. This time is adjustable through the choice of the slew resistors, the external resistors to ground on the RVSL and RCSL pins and the external components used for
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the external voltage feedback capacitor CV (from CAP to the MOSFET drain) and the sense resistor. Lower slew rates (longer slew times, lower frequency for harmonics rolloff) are created with higher values of RVSL, RCSL, CV and the current sense resistor. Setting the voltage and current slew rates should be done empirically. The most practical way of determining these components is to set CV and the sense resistor value. Then, start by making RVSL, RCSL each a 50k resistor pot in series with 3.3k. Starting from the lowest resistor setting (fast slew) adjust the pots until the noise level meets your guidelines. Note that slower slewing waveforms will dissipate more power so that efficiency will drop. You can monitor this as you make your slew adjustment by measuring input and output voltage and their respective currents. Measuring noise should be done carefully. It is easy to introduce noise by poor measurement techniques. Consult AN70 for recommended measurement techniques. Keeping probe ground leads very short is essential. Usually it will be desirable to keep the voltage and current slew resistors approximately the same. There are circumstances where a better optimization can be found by adjusting each separately, but as these values are separated further, a loss of independence of control may occur. It is possible to use a single slew setting resistor. In this case the RVSL and RCSL pins are tied together. A resistor with a value of 1.8k to 34k (one half the individual resistors) can then be tied from these pins to ground. In general only the RCSL value will be available for adjustment of current slew. The current slew time does also depend on the current sense resistor but this resistor is normally set with consideration of the maximum current in the MOSFET. Setting the voltage slew also involves selection of the capacitor CV. The voltage slew time is proportional to the output voltage swing (basically input voltage), the external voltage feedback capacitor and the RVSL value. Thus at higher input voltages smaller capacitors will be used with lower RVSL values. For a starting point use Table 2.
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LT1738
APPLICATIO S I FOR ATIO
Table 2
INPUT VOLTAGE < 25V 50V 100V CAPACITOR VALUE 5pF 2.5pF 1pF
Smaller value capacitors can be made in two ways. The first is simply combining two capacitors in series. The equivalent capacitance is then (C1 * C2)/(C1 + C2). The second method makes use of a capacitor divider. Care should be taken that the voltage rating of the capacitor satisfies the full voltage swing thus essentially the same rating as the MOSFET.
MOSFET DRAIN C2 CAP C3
1738 F02
C1
Figure 2
The equivalent slew capacitance for Figure 2 is (C1 * C2)/(C1 + C2 + C3). Positive Output Voltage Setting Sensing of a positive output voltage is usually done using a resistor divider from the output to the FB pin. The positive input to the error amp is connected internally to a 1.25V bandgap reference. The FB pin will regulate to this voltage. Referring to Figure 3, R1 is determined by: V R1 = R2 OUT - 1 1.25 The FB bias current represents a small error and can usually be ignored for values of R1||R2 up to 10k. One word of caution, sometimes a feedback zero is added to the control loop by placing a capacitor across R1. If the feedback capacitively pulls the FB pin above the internal regulator voltage (2.4V), output regulation may be disrupted. A series resistance with the feedback pin can eliminate this potential problem. There is an internal clamp
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on FB that clamps at 0.7V above the regulation voltage that should also help prevent this problem.
R1 FB PIN R2
1738 F03
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VOUT
Figure 3
Negative Output Voltage Setting Negative output voltage can be sensed using the NFB pin. In this case regulation will occur when the NFB pin is at -2.5V. The nominal input bias current for the NFB is -25A (INFB), which needs to be accounted for in setting up the divider. Referring to Figure 4, R1 is chosen such that:
VOUT - 2.5 R1 = R2 2.5 + R2 * 25A
A suggested value for R2 is 2.5k. The NFB pin is normally left open if the FB pin is being used.
R1 NFB PIN INFB R2
1738 F04
-VOUT
Figure 4
Dual Polarity Output Voltage Sensing Certain applications may benefit from sensing both positive and negative output voltages. When doing this each output voltage resistor divider is individually set as previously described. When both FB and NFB pins are used, the LT1738 will act to prevent either output from going beyond its set output voltage. The highest output (lightest load) will dominate control of the regulator. This technique would prevent either output from going unregulated high at no load. However, this technique will also compromise output load regulation. Shutdown If SHDN is pulled low, the regulator will turn off. As the SHDN pin voltage is increased from ground the internal
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LT1738
APPLICATIO S I FOR ATIO
bandgap regulator will be powered on. This will set a 1.39V threshold for turn on of the internal regulator that runs most of the control circuitry of the regulator. Note after the control circuitry powers on, gate driver activity will depend on the voltage of VIN with respect to the voltage on GCL. As the SHDN pin enables the internal regulator a 24A current will be sourced from the pin that can provide hysteresis for undervoltage lockout. This hysteresis can be used to prevent part shutdown due to input voltage sag from an initial high current draw. In addition to the current hysteresis, there is also approximately 100mV of voltage hysteresis on the SHDN pin. When the SHDN pin is greater than 2.2V, the hysteretic current from the part will be reduced to essentially zero. If a resistor divider is used to set the turn on threshold then the resistors are determined by the following equations
VIN
RB 1.39 = * VON RA * RB VHYST = RA RB * IHYST + 0.1V Reworking these equations yields:
RA SHDN RB
V V - 0.1V RA = ON * HYST IHYST 1.2 VON VHYST - 0.1V RB = * IHYST VON - 1.39
So if we wanted to turn on at 20V with 2V of hysteresis: 20 2 - 0.1 RA = = 1.14M * 1.39 24A 20 2 - 0.1 = 85k RB = * 20 - 1.39 24A Resistor values could be altered further by adding Zeners in the divider string. A resistor in series with SHDN pin could further change hysteresis without changing turn on voltage.
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Frequency Compensation Loop frequency compensation is accomplished by way of a series RC network on the output of the error amplifier (VC pin).
RVC 2k CVC 0.01F VC PIN CVC2 4.7nF
1738 F06
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Figure 6
Referring to Figure 6, the main pole is formed by capacitor CVC and the output impedance of the error amplifier (approximately 400k). The series resistor RVC creates a "zero" which improves loop stability and transient response. A second capacitor CVC2, typically one-tenth the size of the main compensation capacitor, is sometimes used to reduce the switching frequency ripple on the VC pin. VC pin ripple is caused by output voltage ripple attenuated by the output divider and multiplied by the error amplifier. Without the second capacitor, VC pin ripple is:
VCPINRIPPLE =
1.25 * VRIPPLE * gm * RVC VOUT
where VRIPPLE = Output ripple (VP-P ) gm = Error amplifier transconductance RVC = Series resistor on VC pin VOUT = DC output voltage To prevent irregular switching, VC pin ripple should be kept below 50mVP-P . Worst-case VC pin ripple occurs at maximum output load current and will also be increased if poor quality (high ESR) output capacitors are used. The addition of a 0.0047F capacitor for CVC2 pin reduces switching frequency ripple to only a few millivolts. A low value for RVC will also reduce VC pin ripple, but loop phase margin may be inadequate. Setting Current Limit The sense resistor sets the value for maximum operating current. When the CS pin voltage is 0.1V the gate driver will immediately go low (no slew control). Therefore the
LT1738
APPLICATIO S I FOR ATIO
sense resistor value should be set to RS = 0.1V/ISW(PEAK), where ISW(PEAK) is the peak current in the MOSFET. ISW(PEAK) will depend on the topology and component values and tolerances. Certainly it should be set below the saturation current value for the inductor. If the CS pin voltage is 0.22V in addition to the driver going low, VC and SS will be discharged to ground. This is to provide additional protection in the event of a short circuit. By discharging VC and SS the MOSFET will not be stressed as hard on subsequent cycles since the current trip will be set lower. Turn off of the MOSFET will normally be inhibited for about 100ns at the start of every turn on cycle. This is to prevent noise from interfering with normal operation of the controller. This current sense blanking does not prevent the outputs from being turned off in the event of a fault. Slewing of the gate voltage effectively provides additional blanking. Soft-Start The soft-start pin is used to provide control of switching current during startup. The voltage on the VC pin cannot exceed the voltage on the SS pin. A current source will linearly charge a capacitor on the SS pin. The VC pin voltage will thus ramp up also. The approximate time for the voltage on these pins to ramp up is (1.31V/9A) * CSS or approximately 146ms per F. The soft-start current will be initiated as soon as the part turns on. Soft-start will be reinititated after a short-circuit fault. Thermal Considerations Most of the IC power dissipation is derived from the VIN pin. The VIN current depends on a number of factors including: oscillator frequency; loads on V5; slew settings; gate charge current. Additional power is dissipated if V5 sinks current and during the MOSFET gate discharge. The power dissipation in the IC will be the sum of: 1) The RMS VIN current times VIN 2) V5 RMS sink current times 5V 3) The gate drive's RMS discharge current times voltage.
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Because of the strong VIN component it is advantageous to operate the LT1738 at as low a VIN as possible. It is always recommended that package temperature be measured in each application. The part has an internal thermal shutdown to minimize the chance of IC destruction but this should not replace careful thermal design. The thermal shutdown feature does not protect the external MOSFET. A separate analysis must be done for this device to insure that it is operating within safe limits. Once IC power dissipation, PDIS, is determined die junction temperature is then computed as: TJ = TAMB + PDIS * JA where TAMB is ambient temperature and JA is the package thermal resistance. For the 20-pin SSOP, JA is 100C/W. Choosing The Inductor For a boost converter, inductor selection involves tradeoffs of size, maximum output power, transient response and filtering characteristics. Higher inductor values provide more output power and lower input ripple. However, they are physically larger and can impede transient response. Low inductor values have high magnetizing current, which can reduce maximum power and increase input current ripple. The following procedure can be used to handle these trade-offs: 1. Assume that the average inductor current for a boost converter is equal to load current times VOUT/VIN and decide whether the inductor must withstand continuous overload conditions. If average inductor current at maximum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 1.5A overload condition. Also be aware that boost converters are not short-circuit protected, and under output short conditions, only the available current of the input supply limits inductor current. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so don't omit this step. Powdered iron cores are forgiving
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LT1738
APPLICATIO S I FOR ATIO
because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall in between. The following formula assumes continuous mode operation but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions.
IPEAK
VIN VOUT - VIN V = IOUT OUT + VIN 2 * L * f * VOUT
(
)

L = inductance value VIN = supply voltage VOUT = output voltage I = output current f = oscillator frequency 3. Choose a core geometry. For low EMI problems a closed structure should be used such as a pot core, ER core or toroid (see AN70 appendix I). 4. Select an inductor that can handle peak current, average current (heating effects) and fault current. 5. Finally, double check output voltage ripple. The experts in the Linear Technology Applications department have experience with a wide range of inductor types and can assist you in making a good choice. Capacitors Correct choice of input and output capacitors can be very important to low noise switcher performance. Noise depends more on the ESR of the capacitors. In addition lower ESR can also improve efficiency. Input capacitors must also withstand surges that occur during the switching of some types of loads. Some solid tantalum capacitors can fail under these surge conditions. Design Note 95 offers more information but the following is a brief summary of capacitor types and attributes.
Aluminum Electrolytic: Low cost and higher voltage. They will typically only be used for higher voltage applications. Large values will be needed for low ESR. Specialty Polymer Aluminum: Panasonic has come out with their series CD capacitors. While they are only avail-
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able for voltages below 16V, they have very low ESR and good surge capability.
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Solid Tantalum: Small size and low impedance. Typically the maximum voltage rating is 50V. With large surge currents the capacitor may need to be derated or you need a special type such as the AVX TPS line. OS-CON: Lower impedance than aluminum but only available for 35V or less. Form factor may be a problem. Ceramic: Generally used for high frequency and high voltage bypass. They may resonate with their ESL before ESR becomes dominant.
There are continuous improvements being made in capacitors so consult with manufacturers as to your specific needs. Input Capacitors The input capacitor should have low ESR at high frequencies since this will be an important factor concerning how much conducted noise is generated. There are two separate requirements for input capacitors. The first is for the supply to the part's VIN pin. The VIN pin will provide current for the part itself and the gate charge current. The worst component from an AC point is the gate charge current. The actual peak current depends on gate capacitance and slew rate, being higher for larger values of each. The total current can be estimated by gate charge and frequency of operation. Because of the slewing with this part gate charge is spread out over a longer time period than with a normal FET driver. This reduces capacitance requirements. Typically the current will have spikes of under 100mA located at the gate voltage transitions. This is charge/ discharge to and from the threshold voltage. Most slewing occurs with the gate voltage near threshold. Since the part's VIN will typically be under 15V many options are available for choice of capacitor. Values of input capacitor for just the VIN requirement will typically be in the 50F range with an ESR of under 0.1.
LT1738
APPLICATIO S I FOR ATIO
In addition to the part's supply, decoupling of the supply to the inductor needs to be considered. If this is the same supply as the VIN pin then that capacitor will need to be increased. However, often with this part the inductor supply will be a higher voltage and as such will use a separate capacitor. The transformer decoupling capacitor will see the switch current as ripple. The above switch current computation can be used to estimate the capacity for these capacitors.
CIN = 1 VCAP - ESR ISW(MAX) DC * MIN f
where VCAP is the allowed sag on the input capacitor. ESR is the equivalent series resistance for the cap. In general allowed sag will be a few tenths of a volt. Output Filter Capacitor The output capacitor is chosen both for capacity and ESR. The capacity must supply the load current in the switch off state. While slew control reduces higher frequency components of the ripple current in the capacitor, the capacitor ESR and the magnitude of the output ripple current controls the fundamental component. ESR should also be low to reduce capacitor dissipation. Typically ESR should be below 0.05. The capacitance value can be computed by consideration of desired load ripple, duty cycle and ESR.
C OUT = 1 VOUT - ESR IL(MAX) * DC MIN f
MOSFET Selection There is a wide variety of MOSFETs to choose from for this part. The part will work with either normal threshold (3V to 4V) or logic level threshold devices (1V to 2V). Select a voltage rating to insure under worst-case conditions that the MOSFET will not break down. Next choose an
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RON sufficiently low to meet both the power dissipation capabilities of the MOSFET package as well as overall efficiency needs of the converter. The LT1738 can handle a large range of gate charges. However at very large charge stability may be affected. The power dissipation in the MOSFET depends on several factors. The primary element is I2R heating when the device is on. In addition, power is dissipated when the device is slewing. An estimate for power dissipation is: I2 I2 + 4+ P = VIN * ISR * f + I2 * RON * DC 2 2 3 * I2 VIN - RON * I2 + 4 VSR where I is the average current, I is the ripple current in the switch, ISR is the current slew rate, VSR is the voltage slew rate, f is the oscillator frequency, DC is the duty cycle and RON is the MOSFET on-resistance. Setting GCL Voltage Setting the voltage on the GCL pin depends on what type of MOSFET is used and the desired gate drive undervoltage lockout voltage. First determine the maximum gate drive that you require. Typically you will want it to be at least 2V greater than the maximum threshold. Higher voltages will lower the on resistance and increase efficiency. Be certain to check the maximum allowed gate voltage. Often this is 20V but for some logic threshold MOSFETs it is only 8V to 10V. VGCL needs to be set approximately 0.2V above the desired max gate threshold. In addition VIN needs to be at least 1.6V above the gate voltage. The GCL pin can be tied to VIN which will result in a maximum gate voltage of VIN - 1.6V. This pin also controls undervoltage lockout of the gate drive. The undervoltage lockout will prevent the MOSFET from switching until there is sufficient drive present.
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LT1738
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If GCL is tied to a voltage source or Zener less than 6.8V, the gate drivers will not turn on until VIN exceeds the GCL voltage by 0.8V. For VGCL above 6.5V, the gate drive is insured to be off for VIN < 7.3V and they will be turned on by VGCL + 0.8V. If GCL is tied to VIN, the gate driver is always on (undervoltage lockout is disabled). Approximately 50A of current can be sourced from this pin if VIN > VGCL + 0.8V. This could be used to bias a Zener. The GCL pin has an internal 19V Zener to ground that will provide a failsafe for maximum gate voltage. As an example say we are using a Siliconix Si4480DY which has RDS(ON) rated at 6V. To get 6V, VGCL needs to be set to 6.2V and VIN needs to be at least 7.6V. Gate Driver Considerations In general, the MOSFET should be positioned as close to the part as possible to minimize inductance. When the part is active the gate drive will be pulled low to less than 0.2V. When the part is off, the gate drive contains
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a 40k resistor in series with a diode to ground that will offer passive holdoff protection. If you are using some logic level MOSFETs this might not be sufficient. A resistor may be placed from gate to ground, however the value should be reasonably high to minimize DC losses and possible AC issues. The gate drive source current comes from VIN. The sink current exits through PGND. In general the decoupling cap should be placed close to these two pins. Switching Diodes In general, switching diodes should be Schottky diodes. Size and breakdown voltage depend on the specific converter. A lower forward drop will improve converter efficiency. No other special requirements are needed. More Help AN70 contains information about low noise switchers and measurement of noise and should be consulted. AN19 and AN29 also have general knowledge concerning switching regulators. Also, our Application Department is always ready to lend a helping hand.
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LT1738
PACKAGE DESCRIPTIO
5.20 - 5.38** (0.205 - 0.212)
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
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Dimensions in inches (millimeters) unless otherwise noted.
G Package 20-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
7.07 - 7.33* (0.278 - 0.289) 20 19 18 17 16 15 14 13 12 11
7.65 - 7.90 (0.301 - 0.311)
1 2 3 4 5 6 7 8 9 10 1.73 - 1.99 (0.068 - 0.078)
0 - 8
0.65 (0.0256) BSC
0.25 - 0.38 (0.010 - 0.015)
0.05 - 0.21 (0.002 - 0.008)
G20 SSOP 1098
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LT1738
TYPICAL APPLICATIO
X1 1M 90VAC TO 264VAC 0.1F 250VAC "X2" 1M DANGER: HIGH VOLTAGE L1
X3 100k 2W 7.5V IN755 A 10 17 VIN 14 5 510k 1.5nF 7 165k 51k 19.6k 2N2222 3.9k 3.9k 8 16 15 9 6 SHDN V5 SYNC CT RT RVSL RCSL FB GND SS 13 11 10nF U3 LT1738 CAP GATE CS NC PGND VC GCL 3 0.1F 4 2 1 4 18 20 12 0.068 1/2W 6 5 ISO1 CNY17-3 3 MTP2N60E 15pF 19 NC 10 NFB D4 BA521 470pF 15pF 600V
510k
+
56F 35V
2N2222 51k
UNLESS OTHERWISE NOTED: ALL RESISTORS 1206, 5% BR1: GENERAL INSTRUMENTS W06G C2, C3, C4: SANYO MV-GX
INPUT FILTER IS REQUIRED TO ATTENUATE SWITCHING FREQUENCY HARMONICS AND PASS FCC CLASS B (LT1738 DOES NOT ATTENUATE THESE LOW FREQUENCY HARMONICS) MAIN ADVANTAGE WITH LT1738 IS IT MAKES SUPPRESSING THE HIGH FREQUENCY NOISE AND EMI EASY. THIS IS PARTICULARLY USEFUL FOR MEDICAL DEVICES BECAUSE THE AC LINE TO EARTH GND CAPS ON THE INPUT FILTER CAN BE ELIMINATED; ALLOWING THE DEVICE TO PASS THE EARTH GND LEAKAGE CURRENT MEDICAL SPECIFICATIONS.
RELATED PARTS
PART NUMBER LT1683 LT1425 LT1533 LT1534 LT1576 LT176X Family LT1777 LTC1922-1 DESCRIPTION Ultralow Noise Push-Pull DC/DC Controller Isolated Flyback Switching Regulator Ultralow Noise 1A Switching Regulator Ultralow Noise 2A Switching Regulator 1.5A, 200kHz Step-Down Switching Regulator Low Dropout, Low Noise Linear Regulator Low Noise Step-Down Switching Regulator Synchronous Phase Modulated Full-Bridge Controller COMMENTS Dual Output (Push-Pull) Current Mode Architecture. Excellent Regulation without Transformer "Third Winding" Push-Pull Design for Low Noise Isolated Supplies Ultralow Noise Regulator for Boost Topologies Constant Frequency, 1.21V Reference Voltage 150mA to 3A, SOT-23 to TO-220 Programmable dI/dt; Internally Limited dV/dt Adaptive DirectSenseTM Zero Voltage Switching, 50W to Kilowatts, Synchronous Rectification
DirectSense is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Ultralow Noise 30W Offline Power Supply
+
BR1 100F 400V 200pF 200V P6KE200A 510 1 T1 11 2W 220pF 3 6 7 12 10 +VOUT 12V 2.5A C4 330F 25V - VOUT MUR160 K A A1 A2 C2 330F 25V D1
+ +
C3 330F 25V +
5
8
0.1F 1k 1
1k
VOUT
2
2 COMP U2 REF 8 LT1431 4 COLL RTOP 7 RMIO G-F G-S 6 5 3 V+
38.3k 1% 0.22F 10k 1%
1k
1738 TA02
D1: MBR20200CT L1: HM18-10001 T1: PREMIER MAGNETICS POL-15033
1738i LT/TP 0301 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2001

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